1. Field of the Invention
The present invention relates to a dual port memory device capable of accessing in random and in series a plurality of memory cells in a memory cell array, and more particularly, to an improvement of the arrangement of a data input/output port.
2. Description of the Background Art
In accordance with the development of recent image processing techniques, technical development of three dimensional display of color displays of CRTs for personal computers and CAD systems, and for enlarging/reducing images and multiwindows for screens are in progress.
Various port memory devices have been developed for storing digital video signals under such circumstances. A dual port memory device is known as a random access memory optimized for storing video data, and is capable of random and serial access.
FIG. 5 is a diagram showing the pin connection of such a 4-bit dual port memory device. Referring to FIG. 5, the dual port memory device is separated into two groups, one which is enclosed by the chain dotted line, and the other of the remaining pins. The pins separated by the chain dotted line are used for serial access, and the remaining pins are used for random access. A conventional DRAM is supplied with a port for serial access. This dual port memory comprises the following terminals. The reference characters of the terminals and the signals are identical.
Address terminals A.sub.0 -A.sub.7 receive address signals A.sub.0 -A.sub.7.
A control terminal RAS receives a row address strobe signal RAS.
A control terminal CAS receives a column address strobe signal CAS.
Control terminals WB/WE receive in a time divisional manner a write enable signal WE and a signal WB for specifying write per bit operation. This write per bit operation inhibits writing to a desired bit out of the input data of a plural bit unit.
Control terminals DT/OE receive signals DT/OE for data output of a random data input/output port, and for data transfer between a data register and a memory cell array.
A control terminal SC receives a clock signal SC for controlling the input/output of serial data.
A control terminal SE receives a serial enable signal SE.
Random data input/output terminals W.sub.0 /IO.sub.0 -W.sub.3 /IO.sub.3 receive externally applied data of 4 bits W.sub.0 -W.sub.3, as well as data IO.sub.0 -IO.sub.3 read out from 4 bits of memory cells in a memory cell array.
Serial data input/output terminals SIO.sub.0 -SIO.sub.3 receive externally applied data, as well as data read out in series from a memory cell array.
Power supply terminals V.sub.ss and V.sub.CC receive externally applied power supply voltage.
FIG. 6 is a block diagram of the dual port memory device of FIG. 5. Referring to FIG. 6, the dual port memory device comprises a memory M, an address buffer 2, a random data buffer 5, and a serial data buffer 9, in addition to the connection pins of FIG. 5. Memory M comprises a memory cell array 1 having a plurality of memory cells arranged in the row direction and the column direction, a row decoder 3, a column decoder 4, an address pointer 6, a data register 7, a serial data selector 8, and a clock generator 10. Random data buffer 5, random data input/output terminals W.sub.0 /IO.sub.0 -W.sub.3 /IO.sub.3 implement a random data input/output port W/IO. Serial data buffer 9 and serial data input/output terminals SIO.sub.0 -SIO.sub.3 implement a serial data input/output port SIO. Clock generator 10 responds to various externally applied control signals via a relevant control terminal to generate an internal control signal for controlling the internal circuit. The internal signal is denoted a reference character identical to an externally applied control signal.
Address buffer 2, row decoder 3, column decoder 4, and data buffer 5 are circuits similar to those used in a typical dynamic RAM to carry out random access control. Address pointer 6, data register 7, serial data selector 8, and serial data buffer 9 are circuits for carrying out serial access control.
FIG. 7 is a timing chart of the dual port memory device of FIG. 6. Row address strobe signal RAS, column address strobe signal CAS, and random data W/IO are in asynchronization with clock signal SC and serial data SIO. Random access control and serial access control will be explained with reference to FIGS. 6 and 7.
Random access control is carried out as follows. Row decoder 3 responds to row address strobe signal RAS to strobe a row address signal (refer to FIG. 7(1)). Then, column decoder 4 responds to column address strobe signal CAS to strobe a column address signal (refer to FIG. 7(2)). The strobed row address signal and column address signal are decoded by row decoder 3 and column decoder 4, respectively, and then provided to memory cell array 1. If write enable signal WE and data W.sub.0 -W.sub.3 are applied at this time, data W.sub.0 -W.sub.3 are read into memory cells of 4 bits of memory cell array 1 (refer to FIG. 7(3)). Conversely, if read enable signal OE is applied, data IO.sub.0 -IO.sub.3 are read out from the memory cells of 4 bits of memory cell array 1 (refer to FIG. 7(3)). The readout data are provided from random data input/output port W/IO.
Serial access control is carried out as follows. By address signals A.sub.0 -A.sub.7, row address strobe signal RAS, column address strobe signal CAS, and control signal DT/OE, data stored in the memory cells of 4 bits are transferred to data register 7. At this time, the column address strobed by column address strobe signal CAS is loaded to address pointer 6. The bits (4 bits) specified by the loaded row address are selected by serial data selector 8. The selected 4 bits of data are provided to serial data input/output terminals SIO via serial data buffer 9. Then, address pointer 6 is incremented by 1 point (refer to FIG. 7(4)) every time clock signal SC attains a H level (logical high). This causes the contents of data register 7 to be provided sequentially 1 bit at a time. Thus, the data stored in memory cells of 4 bits in memory cell array 1 are provided to serial data input/output port SIO (refer to FIG. 7(5)). Writing data from serial data input/output port SIO is carried out by an operation in a manner conversely of the reading operation. That is to say, the contents of the serial data input/output port is written sequentially into data register 7 every time clock signal SC attains an H level. Lastly, A.sub.0 -A.sub.7, RAS, CAS, DT/OE control the timing of writing to memory cell array 1.
Thus, the dual port memory can carry out random access and serial access in an asynchronous manner. The inventor of the present invention noticed that noise "a" of FIG. 7(3) is included in the random data at the rise of clock signal SC. This noise "a" may induce erroneous operation of the device that receives data from the dual port memory device. The cause of this noise "a" generation will be explained with reference to FIGS. 8 and 9.
FIG. 8 is a device diagram showing the arrangement of a dual port memory and the power supply wiring. Referring to FIG. 8, this device comprises a semiconductor substrate 20, a memory M, and power supply wirings 21a, 21b. Power supply wirings 21a and 21b are provided in parallel with each other between the inner periphery of semiconductor substrate 20 and the outer periphery of memory M. Between power supply wirings 21a and 21b, random data input/output port W/IO, serial data input/output port SIO, control terminals, power supply terminals V.sub.SS and V.sub.CC, address buffer 2, and input buffer 10a of clock generator 10 are provided.
Power supply wiring 21a is connected to power supply terminal V.sub.CC, and power supply wiring 21b is connected to power supply terminal V.sub.SS. Address buffer 2, random data buffer 5, and serial data buffer 9 receive power supply voltage from power supply wirings 21a and 21b.
A conventional dual port memory device has random data input/output terminals W/IO and serial data input/output terminals SIO mixed both in the right and left directions of power supply terminal V.sub.SS. This means that when clock signal SC attains a H level every time the data provided from random data input/output terminal W/IO is at a L level, the charge in serial data input/output terminal SIO is discharged towards power supply wiring 21a via serial data buffer 9. This discharge current generates voltage by the resistance component of power supply wiring 21a, whereby noise "a" appears in random data input/output port W/IO.
FIG. 9 is a partial enlarged diagram of FIG. 8. Since noise "a" is generated when random data and serial data are output, only the output systems of buffers 5 and 9 will be illustrated, with terminals SIO.sub.3 and W.sub.3 /IO.sub.3. Referring to FIG. 9, random data buffer 5 comprises an inverter 5a, an NOR gate 5b, an NOR gate 5c, an NMOS transistor 5d, and an NMOS transistor 5e. Random data buffer 5 provides data read out from memory M as follows. Inverter 5a inverts data read out from memory M. NOR gate 5b receives data read out from memory M and control signal DT/OE to control MOS transistor 5d. NOR gate 5e receives the data inverted by inverter 5a and control signal DT/OE to control NMOS transistor 5e. NMOS transistor 5d and NMOS transistor 5c are switched complementary to provide the data read out from memory M to random data input/output terminal W.sub.3 /IO.sub.3.
Serial data buffer 9 comprises an inverter 9a, an NOR gate 9b, an NOR gate 9c, an NMOS transistor 9d, and an NMOS transistor 9e. Serial data buffer 9 provides data read out from memory M in series as follows. The data read out from memory M every time clock signal SC attains an H level is inverted by inverter 9a. NOR gate 9b receives the data read out from memory M and control signal SE to control NMOS transistor 9d. NOR gate 9c receives the data inverted by inverter 9a and control signal SE to control NMOS transistor 9e. NMOS transistor 9d and NMOS transistor 9e are switched in a complementary manner to provide data read out from memory M to serial data input/output terminal SIO.sub.3.
When NMOS transistor 9e is turned on, charge stored in serial data input/output terminal SIO.sub.3 flows towards power supply terminal V.sub.SS via power supply wiring 21a (refer to solid line arrow of FIG. 9). This results in the generation of a voltage depending upon the discharge current and resistance component of power supply wiring 21a. If NMOS transistor 5e is at the ON state when this voltage is generated, the generated voltage noise "a" appears on random data input/output terminal W.sub.3 /IO.sub.3.
As described above, noise is generated in the data of the random data input/output terminal in the case where serial data is inverted to a L level when an L level signal is provided from random data input/output terminal in a conventional dual port memory device. To solve this problem, approaches to enlarge the width of the power supply wiring, or to provide separate power supply wirings exclusively for serial access and random access are considered. However, enlargement in the width of the power supply wiring or the increase of the numbers of power supply wirings are not desirable because it will enlarge the area of the semiconductor chip.